DESIGN OF LOW LEAKAGE CURRENT AVERAGE POWER CMOS CURRENT COMPARATOR USING SVL TECHNIQUE WITH PSEUDO NMOS AND TRANSMISSION GATE LOGICS

DESIGN OF LOW LEAKAGE CURRENT AVERAGE POWER CMOS CURRENT COMPARATOR USING SVL TECHNIQUE WITH PSEUDO NMOS AND TRANSMISSION GATE LOGICS

Bibliographic Details
Main Authors: T.R. Dinesh Kumar, K.Mohana Sundaram, M.Anto Bennet, M. Pooja, A.P. Kokila
Format: Article
Language:English
Published: Exeley Inc. 2017-12-01
Series:International Journal on Smart Sensing and Intelligent Systems
Subjects:
current comparator
SVL circuit
pseudo nmos
transmission gate
low power consumption
standby mode.
Online Access:https://www.exeley.com/exeley/journals/in_jour_smart_sensing_and_intelligent_systems/10/5/pdf/10.21307_ijssis-2017-256.pdf

Internet

https://www.exeley.com/exeley/journals/in_jour_smart_sensing_and_intelligent_systems/10/5/pdf/10.21307_ijssis-2017-256.pdf

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