Area efficient digital logic NOT gate using single electron box (SEB)
The continuing scaling down of complementary metal oxide semiconductor (CMOS) has led researchers to build new devices with nano dimensions, whose behavior will be interpreted based on quantum mechanics. Single-electron devices (SEDs) are promising candidates for future VLSI applications, due to the...
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| Format: | Article |
| Language: | English |
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EDP Sciences
2017-01-01
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| Series: | International Journal for Simulation and Multidisciplinary Design Optimization |
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| Online Access: | https://doi.org/10.1051/smdo/2016017 |