Design and analysis of single- ended robust low power 8T SRAM cell

Design and analysis of single- ended robust low power 8T SRAM cell

This paper is based on the observation of 8T single ended static random access memory (SRAM) and two techniques for reducing the sub threshold leakage current, power consumption are examined. In the first technique, effective supply voltage and ground node voltages are changed using a dynamic variab...

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Main Authors: Gupta Neha, Pahuja Hitesh
Format: Article
Language:English
Published: EDP Sciences 2016-01-01
Series:MATEC Web of Conferences
Online Access:http://dx.doi.org/10.1051/matecconf/20165701005
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spelling doaj-04a1535879e74ea2876a45d457452c2b2021-02-02T01:59:20ZengEDP SciencesMATEC Web of Conferences2261-236X2016-01-01570100510.1051/matecconf/20165701005matecconf_icaet2016_01005Design and analysis of single- ended robust low power 8T SRAM cellGupta Neha0Pahuja Hitesh1Research Scholar, CDACMohaliProject Engineer, CDAC MohaliThis paper is based on the observation of 8T single ended static random access memory (SRAM) and two techniques for reducing the sub threshold leakage current, power consumption are examined. In the first technique, effective supply voltage and ground node voltages are changed using a dynamic variable voltage level technique(VVL). In the second technique power supply is scaled down. This 8T SRAM cell uses one word line, two bitlinesand a transmission gate. Simulations and analytical results show that when the two techniques combine the new SRAM cell has correct read and write operation and also the cell contains 55.6% less leakage and the dynamic power is 98.8% less than the 8T single ended SRAM cell. Simulations are performed using cadence virtuoso tool at 45nm technology.http://dx.doi.org/10.1051/matecconf/20165701005
collection DOAJ
language English
format Article
sources DOAJ
author Gupta Neha
Pahuja Hitesh
spellingShingle Gupta Neha
Pahuja Hitesh
Design and analysis of single- ended robust low power 8T SRAM cell
MATEC Web of Conferences
author_facet Gupta Neha
Pahuja Hitesh
author_sort Gupta Neha
title Design and analysis of single- ended robust low power 8T SRAM cell
title_short Design and analysis of single- ended robust low power 8T SRAM cell
title_full Design and analysis of single- ended robust low power 8T SRAM cell
title_fullStr Design and analysis of single- ended robust low power 8T SRAM cell
title_full_unstemmed Design and analysis of single- ended robust low power 8T SRAM cell
title_sort design and analysis of single- ended robust low power 8t sram cell
publisher EDP Sciences
series MATEC Web of Conferences
issn 2261-236X
publishDate 2016-01-01
description This paper is based on the observation of 8T single ended static random access memory (SRAM) and two techniques for reducing the sub threshold leakage current, power consumption are examined. In the first technique, effective supply voltage and ground node voltages are changed using a dynamic variable voltage level technique(VVL). In the second technique power supply is scaled down. This 8T SRAM cell uses one word line, two bitlinesand a transmission gate. Simulations and analytical results show that when the two techniques combine the new SRAM cell has correct read and write operation and also the cell contains 55.6% less leakage and the dynamic power is 98.8% less than the 8T single ended SRAM cell. Simulations are performed using cadence virtuoso tool at 45nm technology.
url http://dx.doi.org/10.1051/matecconf/20165701005
work_keys_str_mv AT guptaneha designandanalysisofsingleendedrobustlowpower8tsramcell
AT pahujahitesh designandanalysisofsingleendedrobustlowpower8tsramcell
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