Applying Partial Power-Gating to Direction-Sliced Network-on-Chip

by Feng Wang, Xiantuo Tang, Zuocheng Xing
Published 2015-01-01

An Improved Concatenation Scheme of BCH-Polar Codes With Low-Latency Decoding Architecture

by Yu Wang, Lirui Chen, Cang Liu, Zuocheng Xing
Published 2019-01-01

Efficient MIMO Preprocessor With Sorting-Relaxed QR Decomposition and Modified Greedy LLL Algorithm

by Lirui Chen, Zuocheng Xing, Yongzhong Li, Shikai Qiu
Published 2020-01-01

High Area-Efficient Parallel Encoder with Compatible Architecture For 5G LDPC Codes

by Yufei Zhu, Zuocheng Xing, Zerun Li, Yang Zhang, Yifan Hu
Published 2021-04-01

An Area-Efficient Hybrid Polar Decoder With Pipelined Architecture

by Yu Wang, Qinglin Wang, Yang Zhang, Shikai Qiu, Zuocheng Xing
Published 2020-01-01

Low latency group‐sorted QR decomposition algorithm for larger‐scale MIMO systems

by Lirui Chen, Yu Wang, Zuocheng Xing, Shikai Qiu, Qinglin Wang, Yongzhong Li
Published 2021-07-01

Area-Efficient Parallel Reconfigurable Stream Processor for Symmetric Cryptograph

by Yufei Zhu, Zuocheng Xing, Jinhui Xue, Zerun Li, Yifan Hu, Yang Zhang, Yongzhong Li
Published 2021-01-01