Showing 1 - 20 results of 58 for search 'Wang-DauhTseng', query time: 0.43s Refine Results
  1. 1
    Design for Testability and Test Strategies of Multichip Modules
    by Wang-Dauh Tseng, 曾王道
    Published 1999
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  2. 2
    Variable Pattern Size Pattern Run-length Coding Based on Fibonacci Number for Test data Compression
    by Hsien-Yi Yang, 楊顯奕
    Published 2018
    Other Authors: “...Wang-Dauh Tseng...”
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  3. 3
    Origami-Based Test Data Compression
    by Hung-Kuo Lai, 賴弘國
    Published 2019
    Other Authors: “...Wang-Dauh Tseng...”
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  4. 4
    Power-Aware Test Data Compression by Pattern Run-Length with Variable Pattern Length
    by Mei-Ling Ho, 何美玲
    Published 2019
    Other Authors: “...Wang-Dauh Tseng...”
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  5. 5
    Arithmetic Progression Segmented Extended Frequency-directed Run-length Coding for Test Data Compression
    by Wan-Chen Hsieh, 謝宛真
    Published 2017
    Other Authors: “...Wang-Dauh Tseng...”
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  6. 6
    Design of Configurable USB Pen Drive
    by Yun Chang Wang, 王韻昌
    Published 2018
    Other Authors: “...Wang-Dauh Tseng...”
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  7. 7
    Cascaded Multicasting Scan Chain Ordering for Test Data Compression
    Other Authors: “...Wang-Dauh Tseng...”
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  8. 8
    A variable block size pattern run-length codingfor test data compression
    by Cheng-Han Lin, 林承翰
    Published 2017
    Other Authors: “...Wang-Dauh Tseng...”
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  9. 9
    Enhanced Multi-Dimensional Pattern Run-Length for Test Data Compression
    by Kuo-Yu Chiu, 邱國煜
    Published 2017
    Other Authors: “...Wang-Dauh Tseng...”
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  10. 10
    TAM Switch Based Test Scheduling for Core-Based SOCs
    by Ya-Jing Wang, 王雅靖
    Published 2003
    Other Authors: “...Wang-Dauh Tseng...”
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  11. 11
    Simultaneous Test Data and Test Power Reduction Using Evolution Algorithm
    by you-an chen, 陳宥安
    Published 2010
    Other Authors: “...Wang-Dauh Tseng...”
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  12. 12
    Scan Chain Partitioning for Low Capture Power Testing
    by Zheng-Yi Xie, 謝政益
    Published 2010
    Other Authors: “...Wang-Dauh Tseng...”
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  13. 13
    Test Data Compression using 2n Pattern Run-length codes
    by Cheng-Ho Chang, 張正和
    Published 2010
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  14. 14
    A Low Power Cascaded Multicasting Architecture for Test Data Compression
    Other Authors: “...Wang-DauhTseng...”
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  15. 15
    Low Power Multi-Output Technique for Test-Per-Scan BIST
    Other Authors: “...Wang-DauhTseng...”
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  16. 16
    Segmented LFSR for Test Data Compres-sion
    Other Authors: “...Wang-Dauh Tseng...”
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  17. 17
    Variable Control Code Multi-Dimensional Pattern Run-Length for Test Data Compression
    Other Authors: “...Wang-Dauh Tseng...”
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  18. 18
    Zero-One LFSR for Low Power Deterministic BIST
    Other Authors: “...Wang-Dauh Tseng...”
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  19. 19
    Featured Pattern Run-Length Coding for Test Data Compression
    Other Authors: “...Wang-Dauh Tseng...”
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  20. 20
    Two-Segment LFSR for Test Data Compression
    Other Authors: “...Wang-Dauh Tseng...”
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