Memory cell simulation on the nanometer scale

by Muller, H. -O, Mizuta, Hiroshi
Published 2000

Design optimization of Coulomb blockade devices

by Muller, H. O., Williams, D., Mizuta, Hiroshi
Published 2001

Coulomb blockade and disorder in 2D quantum dot arrays

by Muller, H. O., Williams, D., Mizuta, Hiroshi
Published 2000

Effects of disorder on the blockade voltage of two-dimensional quantum dot arrays

by Muller, H. -O, Katayama, K., Mizuta, Hiroshi
Published 1998

Simulating Si multiple tunnel junctions from pinch-off to ohmic conductance

by Muller, H. -O, Williams, D., Mizuta, Hiroshi, Durrani, Z. A. K.
Published 2000

Design and analysis of high-speed random access memory with Coulomb blockade charge confinement

by Katayama, K., Mizuta, Hiroshi, Muller, H. -O, Williams, D., Nakazato, K.
Published 1999

Simulation of Si multiple tunnel junctions

by Muller, H. -O, Williams, D., Mizuta, Hiroshi, Durrani, Z. A. K., Irvine, A. C., Ahmed, H.
Published 1999

Origin of yield problems of single electron devices based on evaporated granular films

by Muller, H. -O, Boero, M., Vincent, J. K., Inkson, J. C., Mizuta, Hiroshi, Mulheran, P. A.
Published 1999

Nanoscale Coulomb blockade memory and logic devices

by Mizuta, Hiroshi, Muller, H. O., Tsukagoshi, K., Williams, D., Durrani, Z., Irvine, A., Amakawa, S., Evans, G., Nakazato, K., Ahmed, H.
Published 2001

Fabrication of MOS-integrated metallic single-electron memories

by Pepin, A., Vieu, C., Launois, H., Rosmeulen, M., Rossum, M. van, Muller, H. O., Williams, D., Mizuta, Hiroshi, Nakazato, K.
Published 2000