Correction to “Impact of Microarchitectural Differences of RISC-V Processor Cores on Soft Error Effects”

by Hyungmin Cho
Published 2019-01-01

Correction to “ASIC-Resistance of Multi-Hash Proof-of-Work Mechanisms for Blockchain Consensus Protocols”

by Hyungmin Cho
Published 2019-01-01

Impact of Microarchitectural Differences of RISC-V Processor Cores on Soft Error Effects

by Hyungmin Cho
Published 2018-01-01

ASIC-Resistance of Multi-Hash Proof-of-Work Mechanisms for Blockchain Consensus Protocols

by Hyungmin Cho
Published 2018-01-01

Modeling Application-Level Soft Error Effects for Single-Event Multi-Bit Upsets

by Hyungmin Cho, Kon-Woo Kwon
Published 2019-01-01

Minimal Aliasing Single-Error-Correction Codes for DRAM Reliability Improvement

by Sung-Il Pae, Vivek Kozhikkottu, Dinesh Somasekar, Wei Wu, Shankar Ganesh Ramasubramanian, Melin Dadual, Hyungmin Cho, Kon-Woo Kwon
Published 2021-01-01