Using Dataflow to Optimize Energy Efficiency of Deep Neural Network Accelerators

by Chen, Yu-Hsin, Emer, Joel S, Sze, Vivienne
Published 2021

Accelergy: An Architecture-Level Energy Estimation Methodology for Accelerator Designs

by Wu, Yannan Nellie, Emer, Joel S, Sze, Vivienne
Published 2019

Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks

by Chen, Yu-Hsin, Emer, Joel S., Sze, Vivienne
Published 2016

An Architecture-Level Energy and Area Estimator for Processing-In-Memory Accelerator Designs

by Wu, Yannan Nellie, Sze, Vivienne, Emer, Joel S.
Published 2021

Leveraging latency-insensitivity to ease multiple FPGA design

by Fleming, Kermin Elliott, Pellauer, Michael, Arvind, Arvind, Emer, Joel S
Published 2019

Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks

by Chen, Yu-Hsin, Krishna, Tushar, Emer, Joel S., Sze, Vivienne
Published 2016

Soft connections: Addressing the hardware-design modularity problem

by Pellauer, Michael Ignatius, Emer, Joel S., Adler, Michael, Chiou, Derek
Published 2010

A method to estimate the energy consumption of deep neural networks

by Yang, Tien-Ju, Chen, Yu-Hsin, Emer, Joel S, Sze, Vivienne
Published 2021

How to Evaluate Deep Neural Network Processors: TOPS/W (Alone) Considered Harmful

by Sze, Vivienne, Chen, Yu-Hsin, Yang, Tien-Ju, Emer, Joel S
Published 2021

Towards closing the energy gap between HOG and CNN features for embedded vision

by Suleiman, Amr AbdulZahir, Chen, Yu-Hsin, Emer, Joel S, Sze, Vivienne
Published 2020

A scalable architecture for ordered parallelism

by Emer, Joel, Jeffrey, Mark Christopher, Subramanian, Suvinay, Yan, Cong, Sanchez, Daniel
Published 2017

Towards Closing the Energy Gap Between HOG and CNN Features for Embedded Vision

by Suleiman, Amr AbdulZahir, Chen, Yu-Hsin, Emer, Joel S, Sze, Vivienne
Published 2017

Hardware for Machine Learning: Challenges and Opportunities

by Sze, Vivienne, Chen, Yuhsin, Emer, Joel S, Suleiman, Amr AbdulZahir, Zhang, Zhengdong
Published 2017

Data-centric execution of speculative parallel programs

by Jeffrey, Mark Christopher, Subramanian, Suvinay, Abeydeera, Maleen Hasanka, Sanchez Martin, Daniel, Emer, Joel S
Published 2018

DAGguise: mitigating memory timing side channels

by Deutsch, Peter W, Yang, Yuheng, Bourgeat, Thomas, Drean, Jules, Emer, Joel S, Yan, Mengjia
Published 2022

Progress on photonic tensor processors based on time multiplexing and photoelectric multiplication

by Hamerly, Ryan, Sludds, Alexander, Bernstein, Liane, Sze, Vivienne, Emer, Joel, Soljacic, Marin, Englund, Dirk
Published 2022

Digital Optical Neural Networks for Large-Scale Machine Learning

by Bernstein, Liane, Sludds, Alexander, Hamerly, Ryan M, Sze, Vivienne, Emer, Joel S, Englund, Dirk R.
Published 2021

DAWG: A Defense Against Cache Timing Attacks in Speculative Execution Processors

by Kiriansky, Vladimir L. (Vladimir Lubenov), Lebedev, Ilia A., Amarasinghe, Saman P, Devadas, Srinivas, Emer, Joel S
Published 2020

Harmonizing Speculative and Non-Speculative Execution in Architectures for Ordered Parallelism

by Jeffrey, Mark C., Ying, Victor A., Subramanian, Suvinay, Lee, Hyun Ryong, Emer, Joel, Sanchez, Daniel
Published 2021