Design of a Low on Resistance High Voltage (120V) Novel 3D NLDMOS with Side Isolation Based on 0.35um BCD Process Technology

by Yang Shao-Ming, Sheu Gene, Lee Tzu Chieh, Chien Ting Yao, Wu Chieh Chih, Lin Yun Jung
Published 2018-01-01

Study of impact of LATID on HCI reliability for LDMOS devices

by Chandrashekhar, Sheu Gene, Yang Shao Mingo, Chien Ting Yao, Lin Yun Jung, Wu Chieh Chih, Lee Tzu Chieh
Published 2016-01-01

An Innovated 80V-100V High-Side Side-Isolated N-LDMOS Device

by Yangi Shao Ming, Sheu Gene, Chien Ting Yao, Wu Chieh Chih, Lee Tzu Chieh, Wu Ching Yuan, Lai Chiu Chung
Published 2018-01-01

Analysis of Kirk effect of an innovated high side Side-Isolated N-LDMOS device

by Lai Ciou Jhong, Sheu Gene, Chien Ting Yao, Wu Chieh Chih, Lee Tzu Chieh, Deivasigamani Ravi, Wu Ching Yuan, Chandrashekhar, Yang Shao Ming
Published 2016-01-01