Showing 1 - 20 results of 230 for search '"instruction-level parallelism"', query time: 2.29s Refine Results
  1. 1
    Exploiting instruction-level parallelism in superscalar architecture
    by Collins, Roger
    Published 1995
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  2. 2
    Dependency Collapsing in Instruction-Level Parallel Architectures
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  3. 3
    An Automatic Instruction-Level Parallelization of Machine Code
    by MARINKOVIC, V., POPOVIC, M., DJUKIC, M.
    Published 2018-02-01
    “... as on the validation of this approach. The novel instruction-level parallelization algorithm for assembly code which...”
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    Article
  4. 4
    Instruction Level Parallelism Analysis of Java Bytecode with Folding
    by Chen, Chien-Chung, 陳建忠
    Published 1998
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  5. 5
    Exploring the limitations of fine-grained parallelism for a superscalar architecture
    by Potter, Richard Daniel
    Published 1998
    Subjects: “...Instruction-level parallelism...”
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  6. 6
    Investigating opportunities for instruction-level parallelism for stack machine code
    by Shi, Huibin
    Published 2006
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  7. 7
    Superscalar microprocessor hardware tradeoffs in respect to instruction-level parallelism
    by JIANG,QING-QUAN, 江清泉
    Published 1991
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  8. 8
    Invoking two methods simultaneously for instruction level parallelism in Java
    by Ming-Chun Chou, 周明俊
    Published 2002
    “... processor. Exploitation of instruction-level parallelism is restricted in the range of a single method block...”
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  9. 9
    Software orchestration of instruction level parallelism on tiled processor architectures
    by Lee, Walter (Walter Cheng-Wan)
    Published 2006
    “... level parallelism (ILP) on a TPA. It describes Rawcc, an ILP compiler for Raw, a fully distributed TPA...”
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  10. 10
    Design and evaluation of a technology-scalable architecture for instruction-level parallelism
    by Nagarajan, Ramadass, 1977-
    Published 2008
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  11. 11
    Exploitation of instruction-level parallelism for superscalar processors by the conjugate register file scheme
    by Zhang, Meng Zhou, 張孟洲
    Published 1995
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  12. 12
    Efficient Exploitation of Instruction-Level Parallelism Using An Aggressive Register Mapping Scheme
    by Pai, Wen-Liang, 白文良
    Published 1997
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  13. 13
    High Performance Soft Processor Architectures for Applications with Irregular Data- and Instruction-level Parallelism
    by Aasaraai, Kaveh
    Published 2014
    “... data and/or instruction level parallelism offline. However, applications with irregular parallelism...”
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  14. 14
    A high performance pseudo-multi-core elliptic curve cryptographic processor over GF(2^163)
    by Zhang, Yu
    Published 2010
    Subjects: “...instruction-level parallelism...”
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  15. 15
    COMPARISON OF INSTRUCTION SCHEDULING AND REGISTER ALLOCATION FOR MIPS AND HPL-PD ARCHITECTURE FOR EXPLOITATION OF INSTRUCTION LEVEL PARALLELISM
    by Rajendra Kumar
    Published 2018-01-01
    “... optimization in machine description in trimaran infrastructure for exploitation of Instruction level...”
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    Article
  16. 16
    Um mecanismo de busca especulativa de múltiplos fluxos de instruções
    by Santos, Rafael Ramos dos
    Published 2010
    Subjects: “...Instruction-level parallelism...”
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  17. 17
    Um mecanismo de busca especulativa de múltiplos fluxos de instruções
    by Santos, Rafael Ramos dos
    Published 2010
    Subjects: “...Instruction-level parallelism...”
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  18. 18
    Um mecanismo de busca especulativa de múltiplos fluxos de instruções
    by Santos, Rafael Ramos dos
    Published 2010
    Subjects: “...Instruction-level parallelism...”
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  19. 19
    Compiler-Directed Parallelism Scaling Framework for Performance Constrained Energy Optimization
    by Yung-Cheng Ma
    Published 2020-01-01
    Subjects: “...instruction-level parallelism...”
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    Article
  20. 20
    Scheduling Algorithms for Instruction Set Extended Symmetrical Homogeneous Multiprocessor Systems-on-Chip
    by Montcalm, Michael R.
    Published 2011
    Subjects: “...Instruction level parallelism...”
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