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  1. 201
    DSP-Based Remote Monting System
    by Shen-Yu Peng, 彭勝銪
    Published 1999
    “... Word(VLIW),16 bit fixed-point DSP giving 1600Mips peak performance at 200MHz.System expansion...”
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  2. 202
    Fault injection Tool Development and Its Application Study
    by Cheng-Yeh Lee, 李政曄
    Published 2004
    “.... Those application studies include pipeline processor embedded error detection schemes and VLIW processor...”
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  3. 203
    Code Generation For Unified RISC/DSP Processors
    by Chih-Jung Wei, 魏志榮
    Published 2004
    “... designed a unified RISC/DSP processor, UniCore, for multimedia applications. UniCore has only a VLIW...”
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  4. 204
    Optimizing Performance of Dynamic Delayed Micro-pipeline Architecture in Digital Signal Processing
    by Jar-shin Yan, 嚴嘉鑫
    Published 2000
    “... of the digital signal processing, (as VLIW, pipeline, parellel …etc.) Those technologys improve digital signal...”
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  5. 205
    Code Generation for Complex Processors by Machine Learning
    by Chung-Lin Tang, 唐宗麟
    Published 2005
    “...) to such a complex processor, a new VLIW DSP, called the Parallel Architecture Core (PAC). We examine PAC...”
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  6. 206
    Design and Implementation of Multiple Code-rates LDPC Decoder and Encoder for IEEE 802.15.3c
    by Hung, Shiang-Yu, 洪祥譽
    Published 2010
    “.... Experiment results show that the ADRES architecture based on 16 FUs could outperform conventional VLIW...”
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  7. 207
    O efeito da largura de Fetch no desempenho das arquiteturas super escalar, trace cache e DTSVLIW
    by Freitas, Christian Daros de
    Published 2016
    “... Trace Scheduled VLIW (DTSVLIW) machines, have shown performance comparable to that of Superscalars...”
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  8. 208
    A petri-net model for loop scheduling /
    by Wong, Yue-Bong
    Published 1991
    “..., such as superscalar, VLIW, and superpipeline machines. === In the first part we propose a new loop scheduling...”
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  9. 209
    支援多核心PAC DSP的OpenCL 執行期函式庫
    by Wu, Tung-Yu, 吳東育
    Published 2012
    “... system called PACDUO. The system consists of one MPU and 2 five-way issue VLIW DSPs. Each DSP includes...”
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  10. 210
    Design of Multi-Core Embedded Processor Using Configurable Master-Slave I-Cache Controller
    by Ching-Hsiang Chou, 周經翔
    Published 2006
    “... of the algorithm, the thesis designs a multi-core embedded processor that has VLIW architecture. That can be used...”
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  11. 211
    Fault-Tolerant Verification Platform for Systems Modeled at High Level of Abstraction
    by Geng-Wei Wu, 吳耿偉
    Published 2007
    “...-tolerant VLIW core developed by our team is used to demonstrate the feasibility of our approach...”
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  12. 212
    Design of a Low Power ASIP for Network-on-Chip Routing
    by Zi-Lun Wang, 王子綸
    Published 2005
    “... dissipation, so our low power ASIP design adopts the VLIW architecture by increasing its instruction...”
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  13. 213
    Datapath and memory co-optimization for FPGA-based computation
    by Turkington, Kieron
    Published 2010
    “... developed for VLIW processors, is extended and adapted for application to FPGAs. The outer loop pipelining...”
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  14. 214
    Cluster assignment and instruction scheduling for partitioned register-set machines
    by He, Jingsong
    Published 2009
    “... performance. Many of their successful designs such as VLIW and superscalar machines use multiple functional...”
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  15. 215
    The Study of DSP Coding Techniques on Video Compression
    by Wei-Chiang Peng, 彭瑋強
    Published 2000
    “... on generating effective DSP code for H.263 video codec. Due to the rapid development of powerful VLIW DSP chips...”
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  16. 216
    A Register Allocation Algorithm for Shared and Clustered Hybrid Register Files Organization
    by Jer-Yu Hsu, 許哲宇
    Published 2006
    “...碩士 === 國立清華大學 === 資訊工程學系 === 94 === In VLIW processor design, clustered architecture becomes a...”
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  17. 217
    SoftExplorer: Estimating and Optimizing the Power and Energy Consumption of a C Program for DSP Applications
    “..., for different architectures, from the simple RISC ARM7 to the very complex VLIW DSP TI C64. Important phenomena...”
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  18. 218
    Noise reduction for video signals
    by Li, Xiaoli
    Published 2009
    “...-time software module on a VLIW DSP chip. Both prototypes made the intensive subjective evaluations...”
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  19. 219
    Design and Implementation of A Light-Weight Multithreading DSP
    “.... In this thesis, we propose aVLIW architecture with multi lightweight threads. This DSP is named ”UniCoreVMT...”
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  20. 220
    Υλοποίηση κωδικοποιητή πηγής τύπου ADPCM στον επεξεργαστή σήματος TMS320C6711
    “... TMS320 στην οποία αυτός ανήκει είναι η προχωρημένη Very Long Instruction Word (VLIW) αρχιτεκτονική...”
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