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Showing 181 - 200 results of 262 for search '"VLIW"', query time: 0.46s Refine Results
  1. 181
    A Dual-issue, RISC-based DSP Core with emphasis on Code Density
    by Jeng-Yun Hsu, 徐正運
    Published 2000
    “... and code density. We use VLIW and SIMD techniques in our design to provide higher computation power...”
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  2. 182
    Improved software pipelining for superscalar architectures
    by Wienskoski, Edmar, Jr
    Published 2009
    “... developed to improve pipelining efficiency. Among them, several were proposed for scVLIW machines, and were...”
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  3. 183
    The Implementation of Viterbi Decoder on PACDSP Platform
    by 魏仕勳
    Published 2009
    “... on PACDSP, this work utilizes the techniques of VLIW, SIMD, memory collocation, and register allocation...”
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  4. 184
    An Analytical Model of Vulnerability for Embedded Microprocessors
    by 許書豪
    Published 2008
    “... of the mainstream microprocessors — VLIW (Very Long Instruction Word) processor — as an example, the practical...”
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  5. 185
    Design and Implementation of an Energy-Efficient Programmable Vertex Processor with Ray-Tracing Acceleration
    by Liu, Ruei-Jyun, 劉睿峻
    Published 2012
    “... features: 1) four-issue floating-point VLIW datapath; 2) multilevel pre-TnL and post-TnL vertex cache...”
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  6. 186
    Study of Scalable Architectures on FPGA for Space Data Processors
    by Revuelta Fernández, Borja
    Published 2018
    “...) in the fields of Network-on-Chips (NoC) and floating-point VLIW Digital Signal Processors (DSPs...”
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  7. 187
    An instruction scheduling algorithm for communication-constrained microprocessors
    “... randomized instruction scheduling algorithm designed for communication-constrained VLIW-style machines...”
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  8. 188
    DSP based and implementation of image guidance
    by Shih-Wei Hsu, 許士威
    Published 2009
    “... and navigation strategy. This thesis is based on a CCD image collection module and TMS320C6416 high-order VLIW...”
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  9. 189
    Speedup Power Prediction for the low power Analysis of Fault Tolerant System on Gate-Level
    by 張雲斌
    Published 2006
    “... emphasized by the design of the mobile devices．Therefore，utilizing VLIW architecture to design a high...”
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  10. 190
    Speedup Power Prediction for the Analysis of Fault Tolerant System on Gate-Level
    by Yung-Ping Chang, 張雲斌
    Published 2006
    “... emphasized by the design of the mobile devices．Therefore，utilizing VLIW architecture to design a high...”
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  11. 191
    A Study of the Limits of Parallelism Available in SIMD Processors Through Register Packing
    by Rou-Jia Chen, 陳柔佳
    Published 2014
    “... with VLIW processor; moreover, our register packing allows for a vector-wide load from the SRAM. Such a load...”
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  12. 192
    Design of Energy-Efficient High-Performance ASIP-DSP Platforms
    by Karlsson, Andréas
    Published 2016
    “... superscalar- and VLIW processor design focus has been to improve the throughput of fine-grained instructions...”
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    Doctoral Thesis
  13. 193
    Design Space Exploration of heterogeneous SoC Platforms for a Data-Dominant Application
    by Portero Trujillo, Antoni
    Published 2009
    “... implementaciones mαltiples son posibles: que van desde una parte grande en HW hasta la que se carga en un VLIW. En...”
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    Doctoral Thesis
  14. 194
    A Programmable, Scalable-Throughput Interleaver
    by E. J. C. Rijshouwer, C. H. van Berkel
    Published 2010-01-01
    “... to 8 addresses every clock cycle. The scalable architecture combines SIMD and VLIW concepts...”
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    Article
  15. 195
    A Programmable, Scalable-Throughput Interleaver
    by Rijshouwer EJC, van Berkel CH
    Published 2010-01-01
    “... to 8 addresses every clock cycle. The scalable architecture combines SIMD and VLIW concepts...”
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    Article
  16. 196
    Design of a Multi-Core Multi-thread Floating-Point Processor and Its Application in Computer Graphics
    by Chia-Yu Yeh, 葉家裕
    Published 2011
    “... multiple data (SIMD), very-long-instruction word (VLIW), multi-threading, and/or multi-core. In OpenGL ES...”
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  17. 197
    Energy-Proportional Processor and Instruction Scheduling
    by Wen Shih Chao, 趙文仕
    Published 2011
    “... for low power consumption in Very Long Instruction Word(VLIW) Architecture. But DVS is not efficient in 65...”
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  18. 198
    Message-Passing Lock Mechanism Design for Asynchronous Multicore Processor
    by Hsiao, Pei-Ying, 蕭培穎
    Published 2011
    “...-way VLIW multi-core processor and add a lock management unit into its network. Functionality...”
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  19. 199
    A VILW-Based Post Compilation Framework for Multimedia Embedded DSPs with Hardware Specific Optimizations
    by 鄭孟璿
    Published 2007
    “... system design, the VLIW-based embedded DSPs which need compiler to exploit the ILP become popular...”
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  20. 200
    Evaluation of PAC DSP – Based on Typical DSP Algorithm Kernels
    by Ching-Hsiang Kuo, 郭景翔
    Published 2006
    “... to develop the first VLIW DSP in Taiwan, called PAC (Parallel Architecture Core) DSP. The objective of PACDSP...”
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