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01031 am a22001573u 4500 |
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364712 |
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|a Mohammadat, M.T.
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|a Ali, N.B.Z.
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|a Hussin, F.A.
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|a Zwolinski, M.
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|a Resistive open faults detectability analysis and implications for testing low power nanometric ICs
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|c 2015-03-20.
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|z Get fulltext
|u https://eprints.soton.ac.uk/364712/1/manuscript.pdf
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|a Resistive open faults (ROFs) represent common manufacturing defects in IC interconnects and result in delay faults that cause timing failures and reliability risks. The nonmonotonic dependence of ROF-induced delay faults on the supply voltage (VDD) poses a concern as to whether single-VDD testing will suffice for low power nanometric designs. Our analysis shows multi-VDD tests could be required, depending on the test speed. This knowledge can be exploited in small delay fault testing to reduce the chances of test escapes while minimizing cost.
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