Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture
We propose two new repair techniques for hybrid nano/CMOS computing architecture with lookup table based Boolean logic. Our proposed techniques use tagging mechanism to provide high level of defect tolerance and we present theoretical equations to predict the repair capability including an estimate...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
2011-05.
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| Subjects: | |
| Online Access: | Get fulltext |