Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture

Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture

We propose two new repair techniques for hybrid nano/CMOS computing architecture with lookup table based Boolean logic. Our proposed techniques use tagging mechanism to provide high level of defect tolerance and we present theoretical equations to predict the repair capability including an estimate...

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Bibliographic Details
Main Authors: Srivastava, Saket (Author), Melouki, Aissa (Author), Al-Hashimi, Bashir (Author)
Format: Article
Language:English
Published: 2011-05.
Subjects:
Article
Online Access:Get fulltext
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100 1 0 |a Srivastava, Saket  |e author 
700 1 0 |a Melouki, Aissa  |e author 
700 1 0 |a Al-Hashimi, Bashir  |e author 
245 0 0 |a Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture 
260 |c 2011-05. 
856 |z Get fulltext  |u https://eprints.soton.ac.uk/268583/1/TaggedRepairTechniquesNanoCmosArch.pdf 
520 |a We propose two new repair techniques for hybrid nano/CMOS computing architecture with lookup table based Boolean logic. Our proposed techniques use tagging mechanism to provide high level of defect tolerance and we present theoretical equations to predict the repair capability including an estimate of the repair cost. The repair techniques are efficient in utilization of spare units and capable of targeting upto 20% defect rates, which is higher than recently reported repair techniques. 
655 7 |a Article 

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