New concepts of worst-case delay and yield estimation in asynchronous VLSI circuits
Estimation of asynchronous circuit performances, such as speed, is one of the major reasons that still keeps that design style undeservedly unpopular. A simple logic simulator would be very useful in overcoming this problem if it is used for evaluating the worst-case delays in the paths of an asynch...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
2009-02.
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| Subjects: | |
| Online Access: | Get fulltext |