A low power memoryless ROM design architecture for a direct digital frequency synthesizer
This paper presents a novel, memoryless, read-only memory (ROM) design architecture for a direct digital frequency synthesizer (DDFS). A pipelining technique is proposed to increase the phase accumulator (PA) throughput. However, this technique increases the number of registers as the pipeline stage...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Turkiye Klinikleri Journal of Medical Sciences
2017
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| Subjects: | |
| Online Access: | View Fulltext in Publisher View in Scopus |