Power-Intent Systolic Array Using Modified Parallel Multiplier for Machine Learning Acceleration

• Main Authors: Alkahtani, H.K (Author), Hassnain Mohsan, S.A (Author), Inayat, K. (Author), Iqbal, J. (Author), Mostafa, S.M (Author), Muslim, F.B (Author)
• Format: Article
• Language: English
• Published: MDPI 2023
• Subjects: accelerators; Adders; Array design; Cost reduction; deep learning; Deep learning; Delay costs; Integral part; Learning systems; machine learning; Machine-learning; Modern machines; Parallel multipliers; Power; Power Optimization; power-intent; Power-intent; systolic arrays; Systolic arrays
• Online Access: View Fulltext in Publisher; View in Scopus
• ISBN: 14248220 (ISSN)
• DOI: 10.3390/s23094297

Systolic arrays are an integral part of many modern machine learning (ML) accelerators due to their efficiency in performing matrix multiplication that is a key primitive in modern ML models. Current state-of-the-art in systolic array-based accelerators mainly target area and delay optimizations with power optimization being considered as a secondary target. Very few accelerator designs directly target power optimizations and that too using very complex algorithmic modifications that in turn result in a compromise in the area or delay performance. We present a novel Power-Intent Systolic Array (PI-SA) that is based on the fine-grained power gating of the multiplication and accumulation (MAC) block multiplier inside the processing element of the systolic array, which reduces the design power consumption quite significantly, but with an additional delay cost. To offset the delay cost, we introduce a modified decomposition multiplier to obtain smaller reduction tree and to further improve area and delay, we also replace the carry propagation adder with a carry save adder inside each sub-multiplier. Comparison of the proposed design with the baseline Gemmini naive systolic array design and its variant, i.e., a conventional systolic array design, exhibits a delay reduction of up to 6%, an area improvement of up to 32% and a power reduction of up to 57% for varying accumulator bit-widths. © 2023 by the authors.