A bit-interleaving 12T bitcell with built-in write-assist for sub-threshold SRAM
This paper presents a half-selected robust 12T bitcell with builtin write-assist for sub-threshold SRAM. The proposed 12T bitcell is robust enough in bit-interleaving architecture to enhance soft-error immunity combined with error correction code. The read stability of the proposed bitcell is improv...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Institute of Electronics Information Communication Engineers
2022
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| Subjects: | |
| Online Access: | View Fulltext in Publisher |