A bit-interleaving 12T bitcell with built-in write-assist for sub-threshold SRAM

• Main Authors: Qiao, S. (Author), Shi, D. (Author), Wang, Y. (Author), Yin, J. (Author), Yuan, J. (Author)
• Format: Article
• Language: English
• Published: Institute of Electronics Information Communication Engineers 2022
• Subjects: bitcell; Bitcell; bit-interleaving; Bit-interleaving; Data dependent; Error correction; Error correction codes; Interleaving architecture; Radiation hardening; Read stability; Soft error; SRAM; sub-threshold; Subthreshold; Sub-threshold SRAM; writability; Writability
• Online Access: View Fulltext in Publisher

 This paper presents a half-selected robust 12T bitcell with builtin write-assist for sub-threshold SRAM. The proposed 12T bitcell is robust enough in bit-interleaving architecture to enhance soft-error immunity combined with error correction code. The read stability of the proposed bitcell is improved by read decoupled. The writability is improved by data-dependent supply-cutoff write-assist. Both rowand column f-selected bitcells can hold data stably during write operations. Simulation results based on a standard 55 nm CMOS technology show that the read static noise margin of the proposed bitcell is 16.13x as that of the conventional 6T bitcell. Moreover, the write failure in the sub-threshold region is eliminated. In addition, the leakage consumption is improved by 15.7% compared with 6T bitcell. © 2022 The Institute of Electronics.