Low-Power Detection and Classification for In-Sensor Predictive Maintenance Based on Vibration Monitoring

• Main Authors: Benedetto, L.D (Author), De Vita, A. (Author), Licciardo, G.D (Author), Pau, D. (Author), Vitolo, P. (Author)
• Format: Article
• Language: English
• Published: Institute of Electrical and Electronics Engineers Inc. 2022
• Subjects: Anomaly detection; artificial intelligence; Auto encoders; autoencoder; classification; CMOS integrated circuits; Computation theory; Convolution; Convolutional neural network; Feature extraction; Field programmable gate arrays (FPGA); FPGA; in-sensor computing; In-sensor computing; Integrated circuit design; Low Power; Neural networks; Power detection; Sensor computing; Sensors predictive maintenance; Ultra-low power; ultra-low-power; Vibration monitoring
• Online Access: View Fulltext in Publisher

 In this work, a new custom design of an anomaly detection and classification system is proposed. It is composed of a convolutional Auto-Encoder (AE) hardware design to perform anomaly detection which cooperates with a mixed HW/SW Convolutional Neural Network (CNN) to perform the classification of detected anomalies. The AE features a partial binarization, so that the weights are binarized while the activations, associated to some selected layers, are non-binarized. This has been necessary to meet the severe area and energy constraints that allow it to be integrated on the same die as the MEMS sensors for which it serves as a neural accelerator. The CNN shares the feature extraction module with the AE, whereas a SW classifier is triggered by the AE when a fault is detected, working asynchronously to it. The AE has been mapped on a Xilinx Artix-7 FPGA, featuring an Output Data Rate (ODR) of 365 kHz and achieving a power dissipation of    33 \boldsymbol {\mu }    W/MHz. Logic synthesis has targeted TSMC CMOS 65 nm, 90 nm, and 130 nm standard cells. Best results achieved highlight a power consumption of    38 \boldsymbol {\mu }    W/MHz with an area occupation of 0.49 mm2 when real-time operations are set. These results enable the integration of the complete neural accelerator in the CMOS circuitry that typically sits with the inertial MEMS on the same silicon die. Comparisons with the related works suggest that the proposed system is capable of state-of-the-art performances and accuracy. © 2001-2012 IEEE.