Detecting Unknown Hardware Trojans in Register Transfer Level Leveraging Verilog Conditional Branching Features

Hardware Trojans have concealed modifications to integrated circuits (ICs) that can alter their functions, performance, or security properties. Existing Trojan detection methods are designed primarily to detect Trojans at the gate-level IC abstraction and lower levels, and only a few studies have in...

Full description

Bibliographic Details
Main Authors: Aminanto, M.E (Author), Septafiansyah, D.P (Author), Sutikno, S. (Author), Wijitrisnanto, F. (Author)
Format: Article
Language:English
Published: Institute of Electrical and Electronics Engineers Inc. 2023
Subjects:
RTL
Online Access:View Fulltext in Publisher
View in Scopus
LEADER 02897nam a2200349Ia 4500
001 10.1109-ACCESS.2023.3272034
008 230529s2023 CNT 000 0 und d
020 |a 21693536 (ISSN) 
245 1 0 |a Detecting Unknown Hardware Trojans in Register Transfer Level Leveraging Verilog Conditional Branching Features 
260 0 |b Institute of Electrical and Electronics Engineers Inc.  |c 2023 
300 |a 1 
856 |z View Fulltext in Publisher  |u https://doi.org/10.1109/ACCESS.2023.3272034 
856 |z View in Scopus  |u https://www.scopus.com/inward/record.uri?eid=2-s2.0-85159693411&doi=10.1109%2fACCESS.2023.3272034&partnerID=40&md5=24b34063fc05b7e158bf5969707b25c5 
520 3 |a Hardware Trojans have concealed modifications to integrated circuits (ICs) that can alter their functions, performance, or security properties. Existing Trojan detection methods are designed primarily to detect Trojans at the gate-level IC abstraction and lower levels, and only a few studies have investigated Trojan detection at the register transfer level (RTL). This study presents a novel machine learning-based approach for RTL-level Trojan detection, which leverages conditional statements from Verilog/VHDL code as ML features. Our proposed method has several significant novelties. Firstly, it can detect unknown Trojan instances since we incorporate general features for all Verilog circuits. Second, our approach can detect nontrigger-based Trojans, which are a type of Trojan that is particularly challenging to detect and has not been addressed by many existing techniques. Third, we incorporate feature engineering techniques, including Mutual Information and Person-Coefficient Correlation, to select the best features. We also implement feature scaling with standardization before balancing the data set. Our experimental results demonstrate that our approach achieves an average accuracy of 95.65% in the detection of Trojans, which is higher than previous detection techniques. The method is tested in the Trust-Hub Trojan benchmark RTL design, which demonstrates its effectiveness in detecting a wider range of Trojans at the RTL level. In summary, our novel approach shows great promise for enhancing hardware security by detecting a wider range of Trojans, including previously unseen Trojans, and improving detection accuracy. Author 
650 0 4 |a Benchmark testing 
650 0 4 |a detection 
650 0 4 |a Feature extraction 
650 0 4 |a Hardware 
650 0 4 |a Hardware design languages 
650 0 4 |a hardware trojan 
650 0 4 |a Integrated circuit modeling 
650 0 4 |a Logic gates 
650 0 4 |a machine learning 
650 0 4 |a RTL 
650 0 4 |a Trojan horses 
650 0 4 |a Verilog 
650 0 4 |a VHDL 
700 1 0 |a Aminanto, M.E.  |e author 
700 1 0 |a Septafiansyah, D.P.  |e author 
700 1 0 |a Sutikno, S.  |e author 
700 1 0 |a Wijitrisnanto, F.  |e author 
773 |t IEEE Access