FPGA-accelerated SmartNIC for supporting 5G virtualized Radio Access Network

• Main Authors: Andriolli, N. (Author), Borromeo, J.C (Author), Kondepu, K. (Author), Valcarenghi, L. (Author)
• Format: Article
• Language: English
• Published: Elsevier B.V. 2022
• Subjects: 5G mobile communication systems; Central units; Competition; Control planes; Customer choice; Equipment costs; Field programmable gate arrays (FPGA); Graphics processing unit; Hardware acceleration; Hardware Acceleration; Market competition; Network function virtualization; Next generation networks; Open computing language; OpenCL; Processing time; Radio access networks; Transfer functions; User planes; Virtual reality
• Online Access: View Fulltext in Publisher

 Disaggregated, virtualized, and open next-generation eNodeB (gNB) could bring several benefits to the Next Generation Radio Access Network (NG-RAN) by enabling more market competition and customer choice, lower equipment costs, and improved network performance. This can be achieved through gNB-central unit (CU)-control plane (CP), gNB-CU-user plane (UP) and gNB-distributed unit (DU) separation, CU and DU function virtualization, and zero touch RAN management and control. However, to achieve the performance required by specific foreseen 5G usage scenarios (e.g., Ultra Reliable Low Latency Communications — URLLC), offloading selected disaggregated gNB functions into an accelerated hardware becomes a necessity. To this aim, this study proposes the implementation of 5G DU Low-PHY layer functions into an FPGA-based SmartNIC exploiting the Open Computing Language (OpenCL) framework to facilitate the integration of accelerated 5G functions within the mobile protocol stack. The proposed implementation is compared against (i) a CPU-based OpenAirInterface implementation, and (ii) a GPU-based implementation of IFFT exploiting clfft and cufft libraries. Experimental results show that the different optimization techniques implemented in the proposed solution reduce the Low-PHY processing time and the use of FPGA resources. Moreover, the GPU-based implementation of the cufft and the proposed FPGA-based implementation have a lower processing time and power consumption compared to a CPU-based implementation for up to two cores. Finally, the implementation in a SmartNIC reduces the delay added by the host-to-device communication through the Peripheral Component Interconnect Express (PCIe) interface, considering both functional split options 2 and 7-1. © 2022 The Authors