Increasing EMI Immunity and Linearity of a CMOS 180 nm Voltage-to-Delay Converter

Increasing EMI Immunity and Linearity of a CMOS 180 nm Voltage-to-Delay Converter

This paper presents a voltage-controlled delay unit (VCDU) with a novel architecture allowing for a wide input range of linearity and an improved immunity to electromagnetic interferences. The circuit is based on a current-starved inverter with a biasing technique to extend the input voltage range o...

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Bibliographic Details
Main Authors: Bosio, F.A (Author), Colalongo, L. (Author), Richelli, A. (Author)
Format: Article
Language:English
Published: MDPI 2022
Subjects:
digitally based analog circuits
electromagnetic immunity
time-mode signal processing
voltage-to-time converter
Online Access:View Fulltext in Publisher
Description
Summary:This paper presents a voltage-controlled delay unit (VCDU) with a novel architecture allowing for a wide input range of linearity and an improved immunity to electromagnetic interferences. The circuit is based on a current-starved inverter with a biasing technique to extend the input voltage range of linearity near to the rail-to-rail linearity range. The proposed scheme was designed by UMC 180 nm standard CMOS process and works without power-hungry amplifiers or comparators. It has a voltage supply of 1.8 V and exhibits a rail-to-rail linearity range (0–1.8 V) with an average EMI-induced jitter of only 1% of the nominal delay. © 2022 by the authors. Licensee MDPI, Basel, Switzerland.
ISBN:20799292 (ISSN)
DOI:10.3390/electronics11081177

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