Networks-on-chip: modeling, analysis, and design methodologies.
The growing complexity of System-on-Chip (SoC) designs motivates both academic and industrial researchers to find better solutions for the complexity of the chip-interconnect. For SoC designs that have hundreds of Processing Elements (PEs), a single shared bus can no longer be accepted as an effi...
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| Language: | English en |
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2011
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| Online Access: | http://hdl.handle.net/1828/3633 |