AN IMPROVED METHOD AND APPARATUS FOR AUTOMATED DESIGN AND VERIFICATON OF INTEGRATED CIRCUITS

• Main Author: Nikolic, Dragomir M.
• Format: Others
• Published: UKnowledge 2005
• Online Access: http://uknowledge.uky.edu/gradschool_theses/268; http://uknowledge.uky.edu/cgi/viewcontent.cgi?article=1271&context=gradschool_theses

Electronic Design Automation (EDA) tools have always played an important role in Very Large Scale Integrated (VLSI) Circuit development. Two major linked roles are to reduce total design cycle time of Integrated Circuits (ICs) and increase profitability. Profitability can significantly be increased through quicker development and shorter time to market which in turn can be achieved through design automation. In addition to design cycle time reduction, design automation provides consistency and repeatability, which are critical for capturing and sharing of efficient design methods. Application Specific Integrated Circuit (ASIC) development and verification is a very manual and time consuming process. The objective of this research is to improve a designs parameters, such as silicon area, timing and power, while achieving design cycle time reduction, through design and implementation of a new action and event-driven flow automation tool. This novel approach to providing a quick and easy method for rapid prototyping and automated verification without need for upgrading individual tools, can lead to great design improvements with very limited upfront investment. The automation tool is developed using a range of programming languages including SKILL (a derivative of LISP), C/C++ and Tool Command Language (TCL). Design and implementation, via use of the tool, are verified through hardening of a 32 bit, low power processor core block while showing design cycle time speedup andgt;7x and reduction in total chip area by more than 20%. Supported and used software tools include: Cadence Silicon Ensemble Place and Route, Signal Integrity, Physical Verification, Cross-Talk Analysis and Abstract Generation; Synopsys Static Timing Analysis (STA); Mentor Graphics Physical Verification, Parasitic Resistance and Capacitance (RC) Extraction.