Formal Sequential Equivalence Checking of Digital Systems by Symbolic Simulation
A new approach to sequential verification of designs at different levels of abstraction by symbolic simulation is proposed. The automatic formal verification tool has been used for equivalence checking of structural descriptions at rt-level and their corresponding behavioral specifications. Gate-lev...
| Main Author: | |
|---|---|
| Format: | Others |
| Language: | English en |
| Published: |
2001
|
| Online Access: | http://tuprints.ulb.tu-darmstadt.de/113/1/thesis.pdf Ritter, Gerd <http://tuprints.ulb.tu-darmstadt.de/view/person/Ritter=3AGerd=3A=3A.html> : Formal Sequential Equivalence Checking of Digital Systems by Symbolic Simulation. [Online-Edition] Technische Universität, Darmstadt [Ph.D. Thesis], (2001) |