Countering Aging Effects through Field Gate Sizing
Transistor aging through negative bias temperature instability (NBTI) has become a major lifetime constraint in VLSI circuits. We propose a technique that uses antifuses to widen PMOS transistors later in a circuit?s life cycle to combat aging. Using HSPICE and 70nm BPTM process numbers, we simulate...
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| Format: | Others |
| Language: | en_US |
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2010
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| Online Access: | http://hdl.handle.net/1969.1/ETD-TAMU-2008-12-100 http://hdl.handle.net/1969.1/ETD-TAMU-2008-12-100 |