Maximum and minimum sensitizable timing analysis using data dependent delays
Modern digital designs require high performance and low cost. In this scenario, timing analysis is an essential step for each phase of the integrated circuit design cycle. To minimize the design turn-around time, the ability to correctly predict the timing behavior of the chip is extremely important...
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| Format: | Others |
| Language: | en_US |
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Texas A&M University
2007
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| Online Access: | http://hdl.handle.net/1969.1/5948 |