Parallel algorithms for inductance extraction
In VLSI circuits, signal delays play an important role in design, timing verification and signal integrity checks. These delays are attributed to the presence of parasitic resistance, capacitance and inductance. With increasing clock speed and reducing feature sizes, these delays will be dominated b...
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| Format: | Others |
| Language: | en_US |
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Texas A&M University
2007
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| Online Access: | http://hdl.handle.net/1969.1/5930 |