| Summary: | Integrated circuits manufactured in current technology consist of millions of
transistors with dimensions shrinking into the nanometer range. These small transistors
have quiescent (leakage) currents that are increasingly sensitive to process variations,
which have increased the variation in good-chip quiescent current and consequently
reduced the effectiveness of IDDQ testing. This research proposes the use of a multivariate
statistical technique known as principal component analysis for the purpose of variance
reduction. Outlier analysis is applied to the reduced leakage current values as well as the
good chip leakage current estimate, to identify defective chips. The proposed idea is
evaluated using IDDQ values from multiple wafers of an industrial chip fabricated in 130
nm technology. It is shown that the proposed method achieves significant variance
reduction and identifies many outliers that escape identification by other established
techniques. For example, it identifies many of the absolute outliers in bad
neighborhoods, which are not detected by Nearest Neighbor Residual and Nearest
Current Ratio. It also identifies many of the spatial outliers that pass when using Current
Ratio. The proposed method also identifies both active and passive defects.
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