Fault modeling, delay evaluation and path selection for delay test under process variation in nano-scale VLSI circuits
Delay test in nano-scale VLSI circuits becomes more difficult with shrinking technology feature sizes and rising clock frequencies. In this dissertation, we study three challenging issues in delay test: fault modeling, variational delay evaluation and path selection under process variation. Previous...
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| Format: | Others |
| Language: | en_US |
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Texas A&M University
2006
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| Online Access: | http://hdl.handle.net/1969.1/3234 |