Contention-Aware and Power-Constrained Scheduling for Chip Multicore Processors
The parallel nature of process execution on chip multiprocessors (CMPs) has considerably boosted levels of application performance in the past decade. Generally, a certain number of computing resources are shared among the several cores of a CMP, such as shared last-level caches, shared-buses, and s...
| Main Author: | |
|---|---|
| Format: | Others |
| Published: |
OpenSIUC
2019
|
| Subjects: | |
| Online Access: | https://opensiuc.lib.siu.edu/theses/2620 https://opensiuc.lib.siu.edu/cgi/viewcontent.cgi?article=3635&context=theses |