IMPLEMENTATION OF RECONFIGURABLE COMPUTING CACHE ARCHITECTURE
In a modern microprocessor, a considerable portion of the chip is dedicated to cache memories. However some applications do not utilize all the cache capacity all the time, on the other side these applications may require more computing power than the actual computing capability. To efficiently util...
| Main Author: | |
|---|---|
| Format: | Others |
| Published: |
OpenSIUC
2010
|
| Online Access: | https://opensiuc.lib.siu.edu/theses/336 https://opensiuc.lib.siu.edu/cgi/viewcontent.cgi?article=1343&context=theses |
| Summary: | In a modern microprocessor, a considerable portion of the chip is dedicated to cache memories. However some applications do not utilize all the cache capacity all the time, on the other side these applications may require more computing power than the actual computing capability. To efficiently utilize the on-chip resources, in this project we have designed and implemented the reconfigurable computing cache architecture, this design is implemented as a schematic in Xilinx. In this architecture a part of an L1 data cache is designed as a reconfigurable functional cache which can act as a conventional cache memory module in memory mode and also work as specialized computing that can perform a selective core function whenever such computing capability is required. Using this reconfigurable cache architecture the execution of the core functions of compute intensive applications are accelerated, due to which the execution time and the number of instructions are significantly reduced, which results in the increased performance of the processor. |
|---|