Voltage controlled resistance model for MOS transistors

Voltage controlled resistance model for MOS transistors

The voltage controlled resistance model is developed for a reliable MOS transistor resistance mapping. The model includes both system and local parameters, and incorporates the effect of rise and fall time variations on the gate delay. MOS transistor resistance mapping is applied in logic simulation...

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Bibliographic Details
Main Author: Jia, Joey Zong-yi
Format: Others
Published: PDXScholar 1988
Subjects:
Electric resistance > Mathematical models
Metal oxide semiconductors > Mathematical models
Electrical and Computer Engineering
Online Access:https://pdxscholar.library.pdx.edu/open_access_etds/3802
https://pdxscholar.library.pdx.edu/cgi/viewcontent.cgi?article=4811&context=open_access_etds
Description
Summary:The voltage controlled resistance model is developed for a reliable MOS transistor resistance mapping. The model includes both system and local parameters, and incorporates the effect of rise and fall time variations on the gate delay. MOS transistor resistance mapping is applied in logic simulation and timing verification. Also, it can be used in automatic transistor sizing and critical path analysis.

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