Optimal Network Topologies and Resource Mappings for Heterogeneous Networks-on-Chip
Communication has become a bottleneck for modern microprocessors and multi-core chips because metal wires don't scale. The problem becomes worse as the number of components increases and chips become bigger. Traditional Systems-on-Chips (SoCs) interconnect architectures are based on shared-bus...
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| Format: | Others |
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PDXScholar
2013
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| Online Access: | https://pdxscholar.library.pdx.edu/open_access_etds/997 https://pdxscholar.library.pdx.edu/cgi/viewcontent.cgi?article=1996&context=open_access_etds |