A low level analysis of Cellular Automata and Random Boolean Networks as a computational architecture

With the transition from single-core to multi-core computing and CMOS technology reaching its physical limits, new computing architectures which are scalable, robust, and low-power are required. A promising alternative to conventional computing architectures are Cellular Automata (CA) networks and R...

Full description

Bibliographic Details
Main Author: Damera, Prateen Reddy
Format: Others
Published: PDXScholar 2011
Subjects:
Online Access:https://pdxscholar.library.pdx.edu/open_access_etds/670
https://pdxscholar.library.pdx.edu/cgi/viewcontent.cgi?article=1669&context=open_access_etds
id ndltd-pdx.edu-oai-pdxscholar.library.pdx.edu-open_access_etds-1669
record_format oai_dc
spelling ndltd-pdx.edu-oai-pdxscholar.library.pdx.edu-open_access_etds-16692019-10-20T04:45:36Z A low level analysis of Cellular Automata and Random Boolean Networks as a computational architecture Damera, Prateen Reddy With the transition from single-core to multi-core computing and CMOS technology reaching its physical limits, new computing architectures which are scalable, robust, and low-power are required. A promising alternative to conventional computing architectures are Cellular Automata (CA) networks and Random Boolean Networks (RBN), where simple computational nodes combine to form a network that is capable of performing a larger computational task. It has previously been shown that RBNs can offer superior characteristics over mesh networks in terms of robustness, information processing capabilities, and manufacturing costs while the locally connected computing elements of a CA network provide better scalability and low average interconnect length. This study presents a low level hardware analysis of these architectures using a framework which generates the HDL code and netlist of these networks for various network parameters. The HDL code and netlists are then used to simulate these new computing architectures to estimate the latency, area and power consumed when implemented on silicon and performing a pre-determined computation. We show that for RBNs, information processing is faster compared to a CA network, but CA networks are found to a have lower and better distribution of power dissipation than RBNs because of their regular structure. A well-established task to determine the latency of operation for these architectures is presented for a good understanding of the effect of non-local connections in a network. Programming the nodes for this purpose is done externally using a novel self-configuration algorithm requiring minimal hardware. Configuration for RBNs is done by sending in configuration packets through a randomly chosen node. Logic for identifying the topology for the network is implemented for the nodes in the RBN network to enable compilers to analyze and generate the configuration bit stream for that network. On the other hand, the configuration of the CA network is done by passing in configuration data through the inputs on one of the sides of the cell array and shifting it into the network. A study of the overhead of the network configuration and topology identification mechanisms are presented. An analysis of small-world networks in terms of interconnect power and information propagation capability has been presented. It has been shown that small-world networks, whose randomness lies between that of completely regular and completely irregular networks, are realistic while providing good information propagation capability. This study provides valuable information to help designers make decisions for various performance parameters for both RBN and CA networks, and thus to find the best design for the application under consideration. 2011-01-01T08:00:00Z text application/pdf https://pdxscholar.library.pdx.edu/open_access_etds/670 https://pdxscholar.library.pdx.edu/cgi/viewcontent.cgi?article=1669&context=open_access_etds Dissertations and Theses PDXScholar Nanoarchitecture Random Boolean networks Small-world Networks Computer networks -- Evaluation Computer architecture Cellular automata
collection NDLTD
format Others
sources NDLTD
topic Nanoarchitecture
Random Boolean networks
Small-world Networks
Computer networks -- Evaluation
Computer architecture
Cellular automata
spellingShingle Nanoarchitecture
Random Boolean networks
Small-world Networks
Computer networks -- Evaluation
Computer architecture
Cellular automata
Damera, Prateen Reddy
A low level analysis of Cellular Automata and Random Boolean Networks as a computational architecture
description With the transition from single-core to multi-core computing and CMOS technology reaching its physical limits, new computing architectures which are scalable, robust, and low-power are required. A promising alternative to conventional computing architectures are Cellular Automata (CA) networks and Random Boolean Networks (RBN), where simple computational nodes combine to form a network that is capable of performing a larger computational task. It has previously been shown that RBNs can offer superior characteristics over mesh networks in terms of robustness, information processing capabilities, and manufacturing costs while the locally connected computing elements of a CA network provide better scalability and low average interconnect length. This study presents a low level hardware analysis of these architectures using a framework which generates the HDL code and netlist of these networks for various network parameters. The HDL code and netlists are then used to simulate these new computing architectures to estimate the latency, area and power consumed when implemented on silicon and performing a pre-determined computation. We show that for RBNs, information processing is faster compared to a CA network, but CA networks are found to a have lower and better distribution of power dissipation than RBNs because of their regular structure. A well-established task to determine the latency of operation for these architectures is presented for a good understanding of the effect of non-local connections in a network. Programming the nodes for this purpose is done externally using a novel self-configuration algorithm requiring minimal hardware. Configuration for RBNs is done by sending in configuration packets through a randomly chosen node. Logic for identifying the topology for the network is implemented for the nodes in the RBN network to enable compilers to analyze and generate the configuration bit stream for that network. On the other hand, the configuration of the CA network is done by passing in configuration data through the inputs on one of the sides of the cell array and shifting it into the network. A study of the overhead of the network configuration and topology identification mechanisms are presented. An analysis of small-world networks in terms of interconnect power and information propagation capability has been presented. It has been shown that small-world networks, whose randomness lies between that of completely regular and completely irregular networks, are realistic while providing good information propagation capability. This study provides valuable information to help designers make decisions for various performance parameters for both RBN and CA networks, and thus to find the best design for the application under consideration.
author Damera, Prateen Reddy
author_facet Damera, Prateen Reddy
author_sort Damera, Prateen Reddy
title A low level analysis of Cellular Automata and Random Boolean Networks as a computational architecture
title_short A low level analysis of Cellular Automata and Random Boolean Networks as a computational architecture
title_full A low level analysis of Cellular Automata and Random Boolean Networks as a computational architecture
title_fullStr A low level analysis of Cellular Automata and Random Boolean Networks as a computational architecture
title_full_unstemmed A low level analysis of Cellular Automata and Random Boolean Networks as a computational architecture
title_sort low level analysis of cellular automata and random boolean networks as a computational architecture
publisher PDXScholar
publishDate 2011
url https://pdxscholar.library.pdx.edu/open_access_etds/670
https://pdxscholar.library.pdx.edu/cgi/viewcontent.cgi?article=1669&context=open_access_etds
work_keys_str_mv AT dameraprateenreddy alowlevelanalysisofcellularautomataandrandombooleannetworksasacomputationalarchitecture
AT dameraprateenreddy lowlevelanalysisofcellularautomataandrandombooleannetworksasacomputationalarchitecture
_version_ 1719271603794083840