Register-transfer-level power profiling for system-on-chip power distribution network design and signoff
Abstract. This thesis is a study of how register-transfer-level (RTL) power profiling can help the design and signoff of power distribution network in digital integrated circuits. RTL power profiling is a method which collects RTL power estimation results to a single power profile which then can be...
Main Author: | Hämäläinen, J. (Joona) |
---|---|
Format: | Dissertation |
Language: | English |
Published: |
University of Oulu
2019
|
Online Access: | http://jultika.oulu.fi/Record/nbnfioulu-201905141744 |
Similar Items
-
Mobile Signoff Platform Based on Service-Oriented Architecture
by: WEN-HSIEN LIN, et al.
Published: (2016) -
Register-transfer level power estimation and reduction methodologies of digital system-on-chip building blocks
by: Haataja, M. (Miikka)
Published: (2016) -
Design Automation Tool From SystemC To Register-Transfer Level Verilog With Peak Power Minimization
by: Li-Shiuan Wu, et al.
Published: (2008) -
System-on-a-Chip (SoC) based Hardware Acceleration in Register Transfer Level (RTL) Design
by: Niu, Xinwei
Published: (2012) -
Interconnection-Aware Register Transfer Level Partitioning for Low-Power Datapath
by: Ping-Hsun Yang, et al.
Published: (2006)