Mixed-signal verification of analog IP using Schematic Model Generator and SystemVerilog
Verification is one of the most important aspects of designing an integrated circuit. However, the verification by simulating the device level netlist has become problematic as the mixed-signal circuits have become more complex during the years and therefore, the simulation has become very time cons...
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| Format: | Dissertation |
| Language: | English |
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University of Oulu
2018
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| Online Access: | http://urn.fi/URN:NBN:fi:oulu-201805181834 http://nbn-resolving.de/urn:nbn:fi:oulu-201805181834 |