| Summary: | Approved for public release, distribution is unlimited === Without the protection of atmosphere, space systems have to mitigate radiation effects. Several different technologies are used to deal with different radiation effects in order to keep the space device work properly. One of the radiation effects called Single Event Upset (SEU) can change the state of a component or data on the bus. A single error is possible to cause a system failure if it is not corrected. Besides error correction, a space system also needs the flexibility to be modified or upgraded easily. Consequently, the idea of having a TMR design instantiated in an FPGA to construct a Configurable Fault-Tolerant Processor (CFTP) developed. The TMR, which runs one program in three identical soft-core processors with voters, is a scheme used to mitigate an SEU. The full design of TMR running in an FPGA functions as a System-On-a-Chip (SOC). Both soft-core processor and FPGA offer the CFTP a great flexibility to be reconfigured. A complete TMR design includes some fundamental components besides processors and voters such as the Reconiler, Interrupt, and Error Syndrome Storage Device (ESSD). These components have their unique function in the TMR design. They are created and simulated. Factors that affect test bench-settings like processor pipelining are important to always keep in mind. A component is designed to implement proper functions first. Then it is revised to work with the processor and memory. The full design for the TMR in this thesis proves its ability to detect and correct an SEU. The follow-on research suggested is to improve the efficiency and performance of this design.
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