Test methods and custom hardware for functional testing of a high speed GaAs DRAM

Approved for public release; distribution is unlimited. === The goal of this project is to produce a digital circuit operating near a frequency of 250 MHz to test a new experimental Gallium Arsenide (GaAs) Dynamic Random Access Memory (DRAM). This thesis presents the design of the digital circuit us...

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Bibliographic Details
Main Author:	Butler, Michael P.
Other Authors:	Douglas J. Fouts
Language:	en_US
Published:	Monterey, California. Naval Postgraduate School 2014
Online Access:	http://hdl.handle.net/10945/39922

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spelling	ndltd-nps.edu-oai-calhoun.nps.edu-10945-399222014-12-24T04:04:00Z Test methods and custom hardware for functional testing of a high speed GaAs DRAM Butler, Michael P. Douglas J. Fouts Lee, Chin-Hwa Naval Postgraduate School (U.S.) Department of Electrical and Computer Engineering Approved for public release; distribution is unlimited. The goal of this project is to produce a digital circuit operating near a frequency of 250 MHz to test a new experimental Gallium Arsenide (GaAs) Dynamic Random Access Memory (DRAM). This thesis presents the design of the digital circuit using 'off-the-shelf Emitter Coupled Logic (ECL) and the design of a six layer printed circuit test fixture. The use of ECL is illustrated including general design rules, high speed design considerations, and basic transmission line theory. Finally, the design is laid out, and simulated using commercially available Computer Aided Design (CAD) and Computer Aided Manufacturing (CAM) tools. Examples and shortcomings of schematic capture, logic simulation, PCB design, and auto-routing are discussed as applicable to fabrication of the final product. 2014-03-26T23:23:50Z 2014-03-26T23:23:50Z 1993-09 Thesis http://hdl.handle.net/10945/39922 en_US This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, it may not be copyrighted. Monterey, California. Naval Postgraduate School
collection	NDLTD
language	en_US
sources	NDLTD
description	Approved for public release; distribution is unlimited. === The goal of this project is to produce a digital circuit operating near a frequency of 250 MHz to test a new experimental Gallium Arsenide (GaAs) Dynamic Random Access Memory (DRAM). This thesis presents the design of the digital circuit using 'off-the-shelf Emitter Coupled Logic (ECL) and the design of a six layer printed circuit test fixture. The use of ECL is illustrated including general design rules, high speed design considerations, and basic transmission line theory. Finally, the design is laid out, and simulated using commercially available Computer Aided Design (CAD) and Computer Aided Manufacturing (CAM) tools. Examples and shortcomings of schematic capture, logic simulation, PCB design, and auto-routing are discussed as applicable to fabrication of the final product.
author2	Douglas J. Fouts
author_facet	Douglas J. Fouts Butler, Michael P.
author	Butler, Michael P.
spellingShingle	Butler, Michael P. Test methods and custom hardware for functional testing of a high speed GaAs DRAM
author_sort	Butler, Michael P.
title	Test methods and custom hardware for functional testing of a high speed GaAs DRAM
title_short	Test methods and custom hardware for functional testing of a high speed GaAs DRAM
title_full	Test methods and custom hardware for functional testing of a high speed GaAs DRAM
title_fullStr	Test methods and custom hardware for functional testing of a high speed GaAs DRAM
title_full_unstemmed	Test methods and custom hardware for functional testing of a high speed GaAs DRAM
title_sort	test methods and custom hardware for functional testing of a high speed gaas dram
publisher	Monterey, California. Naval Postgraduate School
publishDate	2014
url	http://hdl.handle.net/10945/39922
work_keys_str_mv	AT butlermichaelp testmethodsandcustomhardwareforfunctionaltestingofahighspeedgaasdram
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Test methods and custom hardware for functional testing of a high speed GaAs DRAM

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