A compile-time approach for chaining and execution control in the AN/UYS-2 parallel signal processor

A compile-time approach for chaining and execution control in the AN/UYS-2 parallel signal processor

Approved for public release; distribution is unlimited. === The AN/UYS-2 represents the U. S. Navy's effort to meet the signal processing demands of the 21st century. It is programmed using the Processing Graph Methodology (PGM), where signal processiog applications are reproented as graphs and...

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Main Author: Bell, Harold A.
Other Authors: Shukla, Shridhar B.
Language:en_US
Published: Monterey, California. Naval Postgraduate School 2014
Online Access:http://hdl.handle.net/10945/38518
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spelling ndltd-nps.edu-oai-calhoun.nps.edu-10945-385182014-11-27T16:19:13Z A compile-time approach for chaining and execution control in the AN/UYS-2 parallel signal processor Bell, Harold A. Shukla, Shridhar B. Zaky, Amr Naval Postgraduate School (U.S.) Electrical and Computer Engineering Approved for public release; distribution is unlimited. The AN/UYS-2 represents the U. S. Navy's effort to meet the signal processing demands of the 21st century. It is programmed using the Processing Graph Methodology (PGM), where signal processiog applications are reproented as graphs and the nodes specify library primitives. Presently the AN/LTYS-2 incorporates a First-Come-First-Serve run-time technique to allocate system resources to support large-grain data-flow execution. While this technique results in low run-time overhead, the system throughput degrades rapidly under high system load. To provide uniform output even under high load, a compile-time technique, called Revolving Cylinder (RC) analysis, is developed further to identify optimal chains and restructure the graph. It is shown by simulation that such chaining and restructuring improve the overall system performance. 2014-01-29T23:37:42Z 2014-01-29T23:37:42Z 1992-06 Thesis http://hdl.handle.net/10945/38518 en_US This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, it may not be copyrighted. Monterey, California. Naval Postgraduate School
collection NDLTD
language en_US
sources NDLTD
description Approved for public release; distribution is unlimited. === The AN/UYS-2 represents the U. S. Navy's effort to meet the signal processing demands of the 21st century. It is programmed using the Processing Graph Methodology (PGM), where signal processiog applications are reproented as graphs and the nodes specify library primitives. Presently the AN/LTYS-2 incorporates a First-Come-First-Serve run-time technique to allocate system resources to support large-grain data-flow execution. While this technique results in low run-time overhead, the system throughput degrades rapidly under high system load. To provide uniform output even under high load, a compile-time technique, called Revolving Cylinder (RC) analysis, is developed further to identify optimal chains and restructure the graph. It is shown by simulation that such chaining and restructuring improve the overall system performance.
author2 Shukla, Shridhar B.
author_facet Shukla, Shridhar B.
Bell, Harold A.
author Bell, Harold A.
spellingShingle Bell, Harold A.
A compile-time approach for chaining and execution control in the AN/UYS-2 parallel signal processor
author_sort Bell, Harold A.
title A compile-time approach for chaining and execution control in the AN/UYS-2 parallel signal processor
title_short A compile-time approach for chaining and execution control in the AN/UYS-2 parallel signal processor
title_full A compile-time approach for chaining and execution control in the AN/UYS-2 parallel signal processor
title_fullStr A compile-time approach for chaining and execution control in the AN/UYS-2 parallel signal processor
title_full_unstemmed A compile-time approach for chaining and execution control in the AN/UYS-2 parallel signal processor
title_sort compile-time approach for chaining and execution control in the an/uys-2 parallel signal processor
publisher Monterey, California. Naval Postgraduate School
publishDate 2014
url http://hdl.handle.net/10945/38518
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AT bellharolda compiletimeapproachforchainingandexecutioncontrolintheanuys2parallelsignalprocessor
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