Implementation of error detection and correction (EDAC) in the Static Random Access Memory (SRAM) aboard Petite Amateur Navy Satellite (PANSAT) [electronic resource]
This thesis documents the design of a bus controller that provides EDAC capability to the SRAM of an Intel M8OC 1 86XL Microprocessor running at 7. 3728 MHz. The system was designed for use during a two-year mission in a low earth orbit on board PANSAT. The system uses standard CMOS components toget...
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| Language: | en_US |
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Monterey, California. Naval Postgraduate School
2013
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| Online Access: | http://hdl.handle.net/10945/35063 |