A design of floating point FFT using Genesil Silicon Compiler.

A design of floating point FFT using Genesil Silicon Compiler.

The hardware of floating-point MULTIPLY, ADD, and SUBTRACT units are designed to support the multiplication, addition, and subtraction operation necessary in the Fast Fourier Transform (FFT). In this thesis, the IEEE floating-point standard is adopted and scaled down to 16 bits, but the exponent is...

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Main Author: Lu, Chung-Kuei.
Other Authors: Yang, Chyan
Language:en_US
Published: Monterey, California. Naval Postgraduate School 2013
Online Access:http://hdl.handle.net/10945/30956
id ndltd-nps.edu-oai-calhoun.nps.edu-10945-30956
record_format oai_dc
spelling ndltd-nps.edu-oai-calhoun.nps.edu-10945-309562014-11-27T16:17:50Z A design of floating point FFT using Genesil Silicon Compiler. Lu, Chung-Kuei. Yang, Chyan Naval Postgraduate School (U.S.) Electrical Engineering The hardware of floating-point MULTIPLY, ADD, and SUBTRACT units are designed to support the multiplication, addition, and subtraction operation necessary in the Fast Fourier Transform (FFT). In this thesis, the IEEE floating-point standard is adopted and scaled down to 16 bits, but the exponent is an excess-8 number represented using radix-2. A 16 bit reduced word size floating-point arithematic unit for high speed signal analysis was implemented. The layout verification, functional simulation, and timing analysis of these units have been performed on the Genesil Silicon Compiler (GSC) system that was developed to overcome the shortcomings of the time consuming custom layout methods. The design of this thesis work can be used for further investigation of the high speed, pipelined floating-point arithmetic units. 2013-04-26T19:02:42Z 2013-04-26T19:02:42Z 1991-06 Thesis http://hdl.handle.net/10945/30956 en_US Approved for public release, distribution unlimited This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, it may not be copyrighted. Monterey, California. Naval Postgraduate School
collection NDLTD
language en_US
sources NDLTD
description The hardware of floating-point MULTIPLY, ADD, and SUBTRACT units are designed to support the multiplication, addition, and subtraction operation necessary in the Fast Fourier Transform (FFT). In this thesis, the IEEE floating-point standard is adopted and scaled down to 16 bits, but the exponent is an excess-8 number represented using radix-2. A 16 bit reduced word size floating-point arithematic unit for high speed signal analysis was implemented. The layout verification, functional simulation, and timing analysis of these units have been performed on the Genesil Silicon Compiler (GSC) system that was developed to overcome the shortcomings of the time consuming custom layout methods. The design of this thesis work can be used for further investigation of the high speed, pipelined floating-point arithmetic units.
author2 Yang, Chyan
author_facet Yang, Chyan
Lu, Chung-Kuei.
author Lu, Chung-Kuei.
spellingShingle Lu, Chung-Kuei.
A design of floating point FFT using Genesil Silicon Compiler.
author_sort Lu, Chung-Kuei.
title A design of floating point FFT using Genesil Silicon Compiler.
title_short A design of floating point FFT using Genesil Silicon Compiler.
title_full A design of floating point FFT using Genesil Silicon Compiler.
title_fullStr A design of floating point FFT using Genesil Silicon Compiler.
title_full_unstemmed A design of floating point FFT using Genesil Silicon Compiler.
title_sort design of floating point fft using genesil silicon compiler.
publisher Monterey, California. Naval Postgraduate School
publishDate 2013
url http://hdl.handle.net/10945/30956
work_keys_str_mv AT luchungkuei adesignoffloatingpointfftusinggenesilsiliconcompiler
AT luchungkuei designoffloatingpointfftusinggenesilsiliconcompiler
_version_ 1716725142395027456

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