| Summary: | The hardware of floating-point MULTIPLY, ADD, and SUBTRACT units are designed to support the multiplication, addition, and subtraction operation necessary in the Fast Fourier Transform (FFT). In this thesis, the IEEE floating-point standard is adopted and scaled down to 16 bits, but the exponent is an excess-8 number represented using radix-2. A 16 bit reduced word size floating-point arithematic unit for high speed signal analysis was implemented. The layout verification, functional simulation, and timing analysis of these units have been performed on the Genesil Silicon Compiler (GSC) system that was developed to overcome the shortcomings of the time consuming custom layout methods. The design of this thesis work can be used for further investigation of the high speed, pipelined floating-point arithmetic units.
|
|---|
