A technique for predictable real-time execution in the AN/UYS-2 parallel signal processing architecture

A technique for predictable real-time execution in the AN/UYS-2 parallel signal processing architecture

Bibliographic Details
Main Author:	Little, Brian S.
Other Authors:	Shukla, Shridhar
Language:	en_US
Published:	Monterey, California. Naval Postgraduate School 2013
Online Access:	http://hdl.handle.net/10945/26805

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