A technique for predictable real-time execution in the AN/UYS-2 parallel signal processing architecture

Bibliographic Details
Main Author: Little, Brian S.
Other Authors: Shukla, Shridhar
Language:en_US
Published: Monterey, California. Naval Postgraduate School 2013
Online Access:http://hdl.handle.net/10945/26805
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spelling ndltd-nps.edu-oai-calhoun.nps.edu-10945-268052014-11-27T16:16:32Z A technique for predictable real-time execution in the AN/UYS-2 parallel signal processing architecture Little, Brian S. Shukla, Shridhar NA NA NA Electrical Engineering 2013-01-23T22:05:58Z 2013-01-23T22:05:58Z 1991-09 Thesis http://hdl.handle.net/10945/26805 o227785631 en_US Monterey, California. Naval Postgraduate School
collection NDLTD
language en_US
sources NDLTD
author2 Shukla, Shridhar
author_facet Shukla, Shridhar
Little, Brian S.
author Little, Brian S.
spellingShingle Little, Brian S.
A technique for predictable real-time execution in the AN/UYS-2 parallel signal processing architecture
author_sort Little, Brian S.
title A technique for predictable real-time execution in the AN/UYS-2 parallel signal processing architecture
title_short A technique for predictable real-time execution in the AN/UYS-2 parallel signal processing architecture
title_full A technique for predictable real-time execution in the AN/UYS-2 parallel signal processing architecture
title_fullStr A technique for predictable real-time execution in the AN/UYS-2 parallel signal processing architecture
title_full_unstemmed A technique for predictable real-time execution in the AN/UYS-2 parallel signal processing architecture
title_sort technique for predictable real-time execution in the an/uys-2 parallel signal processing architecture
publisher Monterey, California. Naval Postgraduate School
publishDate 2013
url http://hdl.handle.net/10945/26805
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