The minimization of multiple valued logic expressions using parallel processors.

The minimization of multiple valued logic expressions using parallel processors.

Bibliographic Details
Main Author:	Oral, Sabri Onur.
Other Authors:	Yang, Chyan
Language:	en_US
Published:	Monterey, California. Naval Postgraduate School 2013
Online Access:	http://hdl.handle.net/10945/26633

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