The minimization of multiple valued logic expressions using parallel processors.
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| Language: | en_US |
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Monterey, California. Naval Postgraduate School
2013
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| Online Access: | http://hdl.handle.net/10945/26633 |
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ndltd-nps.edu-oai-calhoun.nps.edu-10945-26633 |
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ndltd-nps.edu-oai-calhoun.nps.edu-10945-266332014-11-27T16:16:25Z The minimization of multiple valued logic expressions using parallel processors. Oral, Sabri Onur. Yang, Chyan Butler, Jon T. Schoenstadt, Arthur L. NA NA Electrical Engineering;Systems Engineering 2013-01-23T22:03:18Z 2013-01-23T22:03:18Z 1991 Thesis http://hdl.handle.net/10945/26633 ocn640387003 en_US Monterey, California. Naval Postgraduate School |
| collection |
NDLTD |
| language |
en_US |
| sources |
NDLTD |
| author2 |
Yang, Chyan |
| author_facet |
Yang, Chyan Oral, Sabri Onur. |
| author |
Oral, Sabri Onur. |
| spellingShingle |
Oral, Sabri Onur. The minimization of multiple valued logic expressions using parallel processors. |
| author_sort |
Oral, Sabri Onur. |
| title |
The minimization of multiple valued logic expressions using parallel processors. |
| title_short |
The minimization of multiple valued logic expressions using parallel processors. |
| title_full |
The minimization of multiple valued logic expressions using parallel processors. |
| title_fullStr |
The minimization of multiple valued logic expressions using parallel processors. |
| title_full_unstemmed |
The minimization of multiple valued logic expressions using parallel processors. |
| title_sort |
minimization of multiple valued logic expressions using parallel processors. |
| publisher |
Monterey, California. Naval Postgraduate School |
| publishDate |
2013 |
| url |
http://hdl.handle.net/10945/26633 |
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AT oralsabrionur theminimizationofmultiplevaluedlogicexpressionsusingparallelprocessors AT oralsabrionur minimizationofmultiplevaluedlogicexpressionsusingparallelprocessors |
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1716724697408733184 |