An investigation of memory latency reduction using an address prediction buffer

Bibliographic Details
Main Author:	Fouts, Douglas J.
Other Authors:	Fouts, Douglas
Language:	en_US
Published:	Monterey, California. Naval Postgraduate School 2012
Online Access:	http://hdl.handle.net/10945/23712

id	ndltd-nps.edu-oai-calhoun.nps.edu-10945-23712
record_format	oai_dc
spelling	ndltd-nps.edu-oai-calhoun.nps.edu-10945-237122014-11-27T16:15:29Z An investigation of memory latency reduction using an address prediction buffer Fouts, Douglas J. Fouts, Douglas NA NA NA NA 2012-11-29T16:14:54Z 2012-11-29T16:14:54Z 1992 Thesis http://hdl.handle.net/10945/23712 ocn640406931 en_US Monterey, California. Naval Postgraduate School
collection	NDLTD
language	en_US
sources	NDLTD
author2	Fouts, Douglas
author_facet	Fouts, Douglas Fouts, Douglas J.
author	Fouts, Douglas J.
spellingShingle	Fouts, Douglas J. An investigation of memory latency reduction using an address prediction buffer
author_sort	Fouts, Douglas J.
title	An investigation of memory latency reduction using an address prediction buffer
title_short	An investigation of memory latency reduction using an address prediction buffer
title_full	An investigation of memory latency reduction using an address prediction buffer
title_fullStr	An investigation of memory latency reduction using an address prediction buffer
title_full_unstemmed	An investigation of memory latency reduction using an address prediction buffer
title_sort	investigation of memory latency reduction using an address prediction buffer
publisher	Monterey, California. Naval Postgraduate School
publishDate	2012
url	http://hdl.handle.net/10945/23712
work_keys_str_mv	AT foutsdouglasj aninvestigationofmemorylatencyreductionusinganaddresspredictionbuffer AT foutsdouglasj investigationofmemorylatencyreductionusinganaddresspredictionbuffer
_version_	1716724334238629888

An investigation of memory latency reduction using an address prediction buffer

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